View SDN8080G_1426453.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet (v6) 2005 sep 29 SDN8080G 80-outputs common/segment driver to improve design and/or performance, avant electronics may make changes to its products. please contac t avant electronics for the latest versions of its products d a t a sh eet
2005 sep 29 2 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 1general 1.1 description the SDN8080G is a common/segmemt driver for large-panel dot-matrix stn lcd module. it can be used either as a common driver or as a segment driver, by connecting its cs input to vdd or vss. when its cs input is connected to vdd, the SDN8080G is an 80-common driver. when it s cs input is connected to vss, the SDN8080G is an 80-segment driver. 1.2 features ? operating voltage range (vdd-vss, control logic): 2.7 ~ 5.5 volts. ? lcd bias voltage range (vdd-vee): 6 ~ 28 volts. ? 80-segment driver or 80-common driver, via cs-pin selection. ? when used as a segment driver, 4-bit parallel or 1-bit serial interface with a controller. ? when used as a common driver, two modes of operation are availabl e: single mode or dual mode. ? display duty cycle: 1/64 ~ 1/256. ? lcd on/off control, when used as segment driver. ? external 4-level lcd bias voltage. ? operating frequency range: 8 mhz, when vdd= 5 volts. ? operating temperature range: -30 to +85 c. ? storage temperature range: -55 to +150 c.
2005 sep 29 3 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 2 ordering information table 1 ordering information type number description SDN8080G-lqfpg lqfp100 pb-free package. SDN8080G-qfpg qfp100 pb-free package. SDN8080G-lqfp lqfp100 general package. SDN8080G-qfp qfp100 general package. SDN8080G-d tested die.
2005 sep 29 4 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 3 functional block diagram and description 3.1 functional block diagram fig.1 functional diagram v0 v12 v43 v5 clock control power down function 80-bit 4-level driver 80-bit level shifter 80-bit data latch / bi-directional shift register for common data 20 x 4-bit (or 80 x 1-bit) bi-directional data latch control vdd vss cs ams cl1 cl2 sck lck m dispoffb vee sc1 sc2 sc3 sc78 sc79 sc80 elb d1_sid d2_dl d3_dm d4_dr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - erb shift register for segment data output voltage level high-voltage area
2005 sep 29 5 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 3.2 block description table 2 block description name com/seg description clock control com/seg inputs to this block are external signa ls cl1, cl2, cs, and ams. it generates latch clock (lck) and shift clock (sck). sck is used to shift display data into the 20 x 4-bit bi-directional sh ift register for segment data. data latch control seg this block controls shift direction of th e 20 x 4-bit shift register and selects its input data pins. in common driver application, this block is disabled. power down function seg this block enables or disables clo ck control block according to erb/elb input. output level selector com/seg controls the output voltage level according to input signals m and dispoffb. 20 x 4-bit bi-directional shift register for segment data seg this is the bi-directional 20 x 4-bit (80-bits) shift register for segmemt data. in 1-bit serial interface mode of segmen driver application, 80 sck clocks are needed to shift in 80-bit data. in 4-bit parallel interface mode, only 20 sck clocks are needed to shift in 80-bit data. in common driver application, this block is disabled. 80-bit data latch, or bi-directional shift register for common data com/seg in segment driver application, this bl ock is used as an 80-bit data latch and the 80-bit data of the segment driver are latched into this latch for output. in single type common driver application, this block is used as an 80-bit shift register. depending on the value of shl, 1-bit serial data is shifted into d2_dl or d4_dr. in dual type common driver applicatio n, depending on the value of shl, the 80-bits shift register is divided into two sections with each section having 40-bits. data are then shifted into the shift register via d2_dl and d3_dm, or d3_dm and d4_dr. please refer to table 6 and table 7 . 80-bit level shifter seg this block translates signals from logical voltage to high voltage for driving the stn lcd panel. 80-bit 4-level driver seg selects output voltage levels according to m and the latched data value.
2005 sep 29 6 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 4 pinning diagrams 4.1 pinning diagram of lqfp100 package fig.2 pin assignment of the lqfp100 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 88 26 27 28 29 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 49 50 38 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 55 56 54 53 52 51 SDN8080G-lqfp sc53 sc54 sc55 sc56 sc57 sc58 sc59 sc60 sc61 sc62 sc64 sc63 sc65 sc66 sc67 sc68 sc70 sc69 sc71 sc72 sc73 sc74 sc75 sc76 sc77 sc27 sc26 sc25 sc24 sc23 sc22 sc21 sc20 sc19 sc18 sc16 sc17 sc15 sc14 sc13 sc12 sc10 sc11 sc9 sc8 sc7 sc6 sc5 sc4 sc3 sc28 sc29 sc30 sc31 sc32 sc33 sc34 sc35 sc36 sc37 sc38 sc39 sc40 sc41 sc42 sc43 sc44 sc45 sc46 sc47 sc48 sc49 sc50 sc51 sc52 sc2 sc1 elb cl1 ams cl2 d1_sid d2_dl d3_dm d4_dr vss shl vdd dispoffb m cs v0 v12 v43 v5 vee erb sc80 sc79 sc78
2005 sep 29 7 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 4.2 pinning diagram of qfp100 package fig.3 pin assignment of the qfp100 package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 49 50 38 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 60 61 59 58 57 56 SDN8080G-qfp100 sc51 sc52 sc53 sc54 sc55 sc56 sc57 sc58 sc59 sc60 sc61 sc62 sc63 sc64 sc65 sc66 sc67 sc68 sc69 sc70 sc71 sc72 sc73 sc74 sc75 sc30 sc29 sc28 sc27 sc26 sc25 sc24 sc23 sc22 sc21 sc20 sc19 sc18 sc17 sc16 sc15 sc14 sc13 sc12 sc11 sc10 sc9 sc8 sc7 sc6 26 27 28 29 30 55 54 53 52 51 sc5 sc4 sc3 sc2 sc1 sc46 sc77 sc78 sc79 sc80 erb vee v5 v43 v12 cs v0 m dispoffb vdd shl d4_dr vss d3_dm d2_dl d1_sid cl2 ams cl1 elb sc50 sc49 sc48 sc47 sc46 sc44 sc45 sc43 sc42 sc41 sc40 sc38 sc39 sc37 sc36 sc35 sc34 sc33 sc32 sc31 100 99 98 97 96 95 94 92 91 90 89 88 87 86 85 84 83 82 81 93
2005 sep 29 8 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 4.3 pad diagram fig.4 pad locations. 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 83 81 80 sc52 sc51 sc50 sc59 sc48 sc47 sc46 sc45 sc44 sc43 sc42 sc41 sc40 sc39 sc38 sc37 sc36 sc35 sc34 sc33 sc32 sc31 sc30 sc29 sc28 31 32 33 34 35 36 37 38 39 40 41 42 43 44 sc78 sc79 sc80 erb vee v5 v43 v12 v0 cs m dispoffb vdd shl vss d4_dr d3_dm d2_dl d1_sid cl2 ams cl1 elb sc1 sc2 46 47 48 49 45 50 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 15 sc77 sc76 sc75 sc74 sc73 sc72 sc71 sc70 sc69 sc68 sc66 sc67 sc65 sc64 sc63 sc62 sc60 sc61 sc59 sc58 sc57 sc56 sc55 sc54 sc53 53 54 55 56 57 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 76 77 65 sc3 sc4 sc5 sc6 sc7 sc8 sc9 sc10 sc11 sc12 sc14 sc13 sc15 sc16 sc17 sc18 sc20 sc19 sc21 sc22 sc23 sc24 sc25 sc26 sc27 78 79 52 51 28 30 (0,0) x y 2 note: 1. for chip_on_board (cob) bonding, chip carrier should be connected to vdd or left open. chip carrier is the metal pad to which die is attached. 2. the chip size is : 2775 p m x 3169 p m. 3. the chip id is: 30001. 29 pad #1 chip id
2005 sep 29 9 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 4.4 pad description table 3 pad signal names and coordinates the unit for coordinates is p m. pad no. pad name coordinates pad no. pad name coordinates pad no. pad name coordinates x y x y x y 1 sc51 -1103 1467 35 v12 -565 -1472 69 sc19 1280 409 2 sc52 -1280 1459 36 v0 -456 -1472 70 sc20 1280 514 3 sc53 -1280 1354 37 cs -331 -1472 71 sc21 1280 619 4 sc54 -1280 1249 38 m -224 -1472 72 sc22 1280 724 5 sc55 -1280 1144 39 dispoffb -118 -1472 73 sc23 1280 829 6 sc56 -1280 1039 40 vdd -12 -1472 74 sc24 1280 934 7 sc57 -1280 934 41 shl 95 -1472 75 sc25 1280 1039 8 sc58 -1280 829 42 vss 208 -1472 76 sc26 1280 1144 9 sc59 -1280 724 43 d4_dr 321 -1472 77 sc27 1280 1249 10 sc60 -1280 619 44 d3_dm 427 -1472 78 sc28 1280 1354 11 sc61 -1280 514 45 d2_dl 534 -1472 79 sc29 1280 1459 12 sc62 -1280 409 46 d1_sid 640 -1472 80 sc30 1102 1467 13 sc63 -1280 304 47 cl2 746 -1472 81 sc31 997 1467 14 sc64 -1280 199 48 ams 853 -1472 82 sc32 892 1467 15 sc65 -1280 94 49 cl1 959 -1472 83 sc33 787 1467 16 sc66 -1280 -11 50 elb 1065 -1472 84 sc34 682 1467 17 sc67 -1280 -116 51 sc1 1280 -1482 85 sc35 577 1467 18 sc68 -1280 -221 52 sc2 1280 -1376 86 sc36 472 1467 19 sc69 -1280 -326 53 sc3 1280 -1271 87 sc37 367 1467 20 sc70 -1280 -431 54 sc4 1280 -1166 88 sc38 262 1467 21 sc71 -1280 -536 55 sc5 1280 -1061 89 sc39 157 1467 22 sc72 -1280 -641 56 sc6 1280 -956 90 sc40 52 1467 23 sc73 -1280 -746 57 sc7 1280 -851 91 sc41 -53 1467 24 sc74 -1280 -851 58 sc8 1280 -746 92 sc42 -158 1467 25 sc75 -1280 -956 59 sc9 1280 -641 93 sc43 -263 1467 26 sc76 -1280 -1061 60 sc10 1280 -536 94 sc44 -368 1467 27 sc77 -1280 -1166 61 sc11 1280 -431 95 sc45 -473 1467 28 sc78 -1280 -1271 62 sc12 1280 -326 96 sc46 -578 1467 29 sc79 -1280 -1376 63 sc13 1280 -221 97 sc47 -683 1467 30 sc80 -1280 -1481 64 sc14 1280 -116 98 sc48 -788 1467 31 erb -1016 -1472 65 sc15 1280 -11 99 sc49 -893 1467 32 vee -894 -1472 66 sc16 1280 94 100 sc50 -998 1467 33 v5 -784 -1472 67 sc17 1280 199 34 v43 -678 -1472 68 sc18 1280 304
2005 sep 29 10 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 4.5 signal description table 4 pad signal description. to avoid a latch-up effect at power-on: v ss 0.5 v < voltage at any pin at any time < v dd + 0.5 v . symbol i/o interface to/from description v0, v12, v43, v5 input power external bias voltage for lcd driver. sc1~sc80 output lcd segment or common driver outputs. cl2 input controller in segment driver application mode, cl2 is the shifting clock of the 20 x 4-bit bi-directional shift register. in common driver application mode, this clock is not used. the display data is shifted to the 80-bit common data bi-directional shift register by cl1. this input has an internal pull-high pm os. when the device is used as common driver, the pmos is turned on to internal ly pull this input to high and this pin should therefore be left open or connected to vdd. please refer to section 13 . m input controller alternating signal for generating alternating lcd-bias voltage. cl1 input controller in segment driver application mode, the 80- bits display data is latched into the shift register at the falling edge of this clock. in common driver application mode, cl1 is used as shifting clock of common output data. dispoffb input controller during the low period of this signal, v0 is selected as sc0~sc80?s outputs and the display is therefore turned off. cs input vdd/vss if cs is connected to vss, the SDN8080G is used as an 80-output segment driver. if cs is connected to vdd, the sd n8080g is used as an 80-output common driver. ams input vdd/vss application mode selection. together with cs input, this input is used to configure SDN8080G into different application modes, as shown in the following table. cs ams application mode com/seg 00 4-bit parallel data interface with a controller. seg 01 1-bit serial data interface with a controller. 1 0 single-type application mode com 1 1 dual-type application mode
2005 sep 29 11 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics d1_sid, d2_dl, d3_dm, d4_dr i/o, d2, d4. input, d1, d3 controller in segment driver mode and when 4-bit parallel data interface mode is selected, these 4 inputs are used as 4-bit parallel data input from a controller. in segment driver mode and when 1-bit serial interface mode is selected, d1_sid is used as serial data input from a controller. in this application, all other 3 inputs must be connected to vdd. in common driver mode and when singl e-type application mode is selected, common scan pulse is shifted from d2_dl to d4_dr or from d4_dr to d2_dl, depending on the logic state of shl. in common driver mode and when dual -type application mode is selected, common scan pulse is shifted from d 2_dl and d3_dm to d4_dr, or from d4_dr and d3_dm to d2_dl, depending on the logic state of shl. shl input vdd/vss shift direction control. when this input is connected to vss, data shift direction is from left to right. when this input is connected to vdd, data shift di rection is from right to left. please refer to table 6 and table 7 . elb, erb input/ output cascade in order to reduce power consumption, in segmentdriver application mode, the internal operation of the SDN8080G is enabled only when its enable input (elb or erb) is at ?low?. when several sdn8 080g are connected in cascade, their enable inputs(elb or erb) are serial ly enabled. the enabling sequence is decided by shl, as listed below. shl segment driver elb erb l output input h input output in common driver application, these two pins are not used and should be left open. symbol i/o interface to/from description
2005 sep 29 12 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 5 output voltage level table 5 output voltage level m latched data dispoffb output level(sc1-sc80) segment mode output level(sc1-sc80) common mode l l h v12(v2) v12(v1) l h h v0 v5 h l h v43(v3) v43(v4) h h h v5 v0 x(don?t care) x(don?t care) l v0 v0
2005 sep 29 13 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 6 lcd bias voltage 6.1 segment driver application (cs=low) fig.5 segment driver application. v0 v12 v43 v5 vss vdd to com driver to com driver v0 v1 v2 v3 v4 v5 c r vdd vdd r r r to lcd panel vee SDN8080G seg1~seg80 n= 9 (when 1/64 duty) to 17 (when 1/256 duty) v0, v5 selection level v2, v3 non-selection level. c c c c c ( n -4) r note: (1) the recommended value for r is in the range from 1k to 10k ohm. (2) the recommended value for c is 0.1 p f. 6.2 common driver application (cs=high) fig.6 common driver application. v0 v5 vss vdd to seg v0 v1 v2 v3 v4 v5 c r vdd vdd r r r r (n- 4 ) to lcd panel vee driver SDN8080G v43 v12 com1~com80 n= 9 (when 1/64 duty) to 17 when ( 1/256 duty ) v0, v5 selection level v1, v4 non-selection level. c c c c c note: (1) the recommended value for r is in the range from 1k to 10k ohm. (2) the recommended value for c is 0.1 p f.
2005 sep 29 14 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 7 data shift direction and data pin i/o selection table 6 data shift direction in segment driver application (cs=low). ams shl application mode data shift direction input pin(pad) l l 4-bit parallel data interface mode shift direction s c 1 s c 2 s c 3 s c 4 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 8 d1 d2 d3 d4 last data first data 34567890 ^ d1 d2 d3 d4 d4 d3 d2 d1 d4 d3 d2 d1 d1_sid, d2_dl, d3_dm, d4_dr h shift direction s c 1 s c 2 s c 3 s c 4 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 8 d1 d2 d3 d4 34567890 first data ^ d1 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 last data h l 1-bit serial data interface mode s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 8 34567890 s c 1 s c 2 s c 3 s c 4 shift direction first data last data (d1_sid) d1_sid h s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 7 s c 8 34567890 s c 1 s c 2 s c 3 s c 4 shift direction first data last data (d1_sid)
2005 sep 29 15 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics table 7 data shift direction in commo n driver application (cs=high) ams shl application mode data shift direction input pin(pad) l l single-type application mode s c 1 s c 2 s c 3 s c 3 s c 3 s c 4 s c 4 s c 4 s c 4 s c 7 s c 7 s c 8 890123 890 shift direction input data (d2_dl) output data (d4_dr) d2_dl h s c 1 s c 2 s c 3 s c 3 s c 3 s c 4 s c 4 s c 4 s c 4 s c 7 s c 7 s c 8 890123 890 shift direction output data (d2_dl) input data (d4_dr) d4_dr h l dual-type application mode s c 1 s c 2 s c 3 s c 3 s c 3 s c 4 s c 4 s c 4 s c 4 s c 7 s c 7 s c 8 890123 890 shift direction input data1 (d2_dl) output data (d4_dr) input data2 (d3_dm) d2_dl, d3_dm h s c 1 s c 2 s c 3 s c 3 s c 3 s c 4 s c 4 s c 4 s c 4 s c 7 s c 7 s c 8 890123 890 shift direction output data (d2_dl) input data1 (d4_dr) input data2 (d3_dm) d4_dr, d3_dm
2005 sep 29 16 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics table 8 application of i/o data pins d 1_sid, d2_dl, d3_dm, and d4_dr com/seg (cs pin) application mode (ams pin) shl data interface pins d1_sid d2_dl d3_dm d4_dr seg (cs=low) 4-bit parallel interface mode (ams=low) x d1 (input) d2 (input) d3 (input) d4 (input) 1-bit serial interface mode (ams=high) x d1_sid connected to vdd. com (cs=high) single-type application mode (ams=low) l open d2_dl (input) open d4_dr (output) h d2_dl (output) d4_dr (input) dual-type application mode (ams=high) l open d2_dl (input1) d3_dm (input2) d2_dr (output2) h d2_dl (output2) d3_dm (input2) d4_dr (input1) .
2005 sep 29 17 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 8 electrical characteristics 8.1 absolute maximum rating table 9 absolute maximum rating symbol parameter min. max. unit v dd voltage on the vdd input. 0.3 +7.0 v v lcd voltage difference between vdd and vee. 0.0 +30.0 v v i (note 1 ) input voltage on any pin with respect to v ss 0.3 v dd + 0.3 v i i , i o input/output current on any i/o pin r 15 ma p tot total power dissipation (note 2) 1.5 w t stg storage temperature range 55 +150 q c t amb operating ambient temperature range. -30 + 85 q c notes 1. the following applies to the absolute maximum ratings: a) stresses above those listed under absolute maximu m ratings may cause permanent damage to the device. b) this product includes circuitry spec ifically designed for the protection of its internal devices from the damaging effect of excessive static charge. however, it is su ggested that conventional pr ecautions be taken to avoid applying greater than the rated maxima. c) parameters are valid over operating temperature range unl ess otherwise specified. al l voltages are with respect to v ss unless otherwise noted. 2. this value is based on the maximum allowable die tem perature and the thermal resistance of the package, not on device power consumption.
2005 sep 29 18 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 8.2 dc characteristics for segment driver application table 10 dc characteristics for segment driver application v dd = 5 v r 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = 0 to +85 q c. symbol parameter conditions min. max. unit v dd supply voltage control logic circuit 2.7 5.5 v v lcd supply voltage for lcd v lcd = vdd - vee 6 28 v v il low level input voltage note 1 0 0.2v dd v v ih high level input voltage note 1 0.8v dd v dd v v ol low level output voltage i ol = 0.4 ma; note 2 0.4 v v oh high level output voltage i oh = -0.4 ma; note 2 v dd v i li1 input leakage current of input pins note 1 10 p a i li2 input leakage current of v0~v5 note 3 +25 p a i stby standby current at vdd=5 volts note 4 100 p a i stby standby current at vdd=3 volts note 5 100 p a i dd(vdd=5v) operating current at vdd=5 volts note 6 5 ma i dd(vdd=3v) operating current at vdd=3 volts note 7 2 ma i ee high-voltage operating current. note 8 500 p a r on on resistance i on = 100 p a, note 9 2k (typ.), 4k (max.) : notes to the dc characteristics: 1. measured for the following pins: cl1, cl2, elb, erb, d1_sid, d2_dl, d3_dm, d4_dr, shl, dispoffb, m, cs, and ams. 2. measured for the erb pin and the elb pin. 3. measured for v0, v12, v43, and v5. 4. conditions for the measurement: vdd=5v, v0=vdd, v12=1.71 v, v43= -19.71 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =5.12 mhz, shl=vss, displayoffb=vdd, m=vss, ams= 0, no-load condition (1/256 duty, 1/17 bias), display data pattern= 0000. 5. conditions for the measurement: vdd=3v, v0=vdd, v12=-0.06 v, v 43= -19.94 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =5.12 mhz, shl=vss, displayoffb=vdd, m=vss, ams= 0, no-load condition (1/256 duty, 1/17 bias), display data pattern= 0000. 6. conditions for the measurement: vdd=5v, v0=vdd, v12=1.71 v, v43= -19.71 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =5.12 mhz, shl=vss, displayoffb=vdd, f m =80 hz, ams=0, no-load conditi on (1/256 duty, 1/17 bias), display data pattern= 01010. 7. conditions for the measurement: vdd=3v, v0=vdd, v12=-0.06 v, v 43= -19.94 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =4 mhz, shl=vss, displayoffb=vdd, f m =80 hz, ams=0, no-load condition (1/256 duty, 1/17 bias), display data pattern= 01010. 8. conditions for the measurement: vdd=5v, v0=vdd, v12=1.71 v, v43= -19.71 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =5.12 mhz, shl=vss, displayoffb=vdd, f m =80 hz, ams=0, no-load conditi on (1/256 duty, 1/17 bias), display data pattern= 01010. measured at vee pin. 9. conditions for the measurement: vlcd=vdd-vee, v0=vdd=5v, v5=vee=-23v, v12= vdd - (2/n) x vlcd, v43=vee + (2/n) x vlcd, n=17 (1/256 duty, 1/17 bias).
2005 sep 29 19 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 8.3 dc characteristics for common driver application table 11 dc characteristics for common driver application v dd = 5 v r 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = 0 to +85 q c. symbol parameter conditions min. max. unit v dd supply voltage control logic part 2.7 5.5 v v lcd supply voltage for lcd v lcd = vdd - vee 6 28 v v il low level input voltage note 1 0 0.2v dd v v ih high level input voltage note 1 0.8v dd v dd v v ol low level output voltage i ol = 0.4 ma; note 2 0.4 v v oh high level output voltage i oh = -0.4 ma; note 2 v dd v i li1 input leakage current of input pins note 1 10 p a i li2 input leakage current of v0~v5 pins note 3 +25 p a i li3 input leakage current of input pins with internal pull-up mos. note 4 +25 p a i stby standby current at vdd=5 volts note 5 100 p a i stby standby current at vdd=3 volts note 6 100 p a i dd(vdd=5v) operating current at vdd=5 volts note 7 200 p a i dd(vdd=3v) operating current at vdd=3 volts note 8 120 p a i ee high-voltage operating current. note 9 500 p a r on on resistance i on = 100 p a, note 10 2k (typ.), 4k (max.) : notes to the dc characteristics 1. measured for the following input pins: cl1, d2_d l(when shl=low), d4_dr(when shl=high), shl, dispoffb, m, cs, and ams. 2. measured for the following output pins: d2_dl(when shl=high) and d4_dr(when shl=low). 3. measured for v0, v12, v43, and v5. 4. measured for the following input pins with internal pull-up: cl2, d1_sid, d3_dm(ams=high), elb(shl=low), erb(shl=high). 5. conditions for the measurement: vdd=5v, v0=vdd, v12=3.35 v, v43= -21.35 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =disabled, shl=vss, displayoffb=vdd, d2_dl=m=vss, ams=0, no-load condition (1/256 duty, 1/17 bias), d1_sid=d3_dm=vdd, d4_dr=elb=erb=open. 6. conditions for the measurement: vdd=5v, v0=vdd, v12=1.47 v, v43= -21.47 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =disabled, shl=vss, displayoffb=vdd, d2_dl=m=vss, ams=0, no-load condition (1/256 duty, 1/17 bias), d1_sid=d3_dm=vdd, d4_dr=elb=erb=open. 7. conditions for the measurement: vdd=5v, v0=vdd, v12=3.35 v, v43= -21.35 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =disabled, shl=vss, displayoffb=vdd, d2_dl=vdd, f m =80hz, ams=0, no-load condition (1/256 duty, 1/17 bias), d1_sid=d3_dm=vdd, d4_dr=elb=erb=open. display data pattern= 10000000..., 01000000..., 00100000..., 00010000. 8. conditions for the measurement: vdd=3v, v0=vdd, v12=1.47 v, v43= -21.47 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =disabled, shl=vss, displayoffb=vdd, d2_dl=vdd, f m =80hz, ams=0, no-load condition (1/256 duty, 1/17 bias), d1_sid=d3_dm=vdd, d4_dr=elb=erb=open. display data pattern= 10000000..., 01000000..., 00100000..., 00010000. 9. conditions for the measurement: vdd=5v, v0=vdd, v12=3.35 v, v43= -21.35 v, v5=vee= -23 v, f cl1 =32 khz, f cl2 =disabled, shl=vss, displayoffb=vdd, d2_dl=vdd, f m =80hz, ams=0, no-load condition (1/256 duty, 1/17 bias), d1_sid=d3_dm=vdd, d4_dr=elb=erb=open.
2005 sep 29 20 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics display data pattern= 10000000..., 01000000..., 00100000..., 00010000. measured at the vee pin (that is, current flowing through the vee pad). 10. vlcd= vdd-vee, v0=vdd=5 volts, v5=vee=-23 volts. v12= vdd- (1/n) x vlcd, v43= vee+ (1/n) x vlcd, n=17(1/256 duty, 1/17 bias). 8.4 ac characteristics for segment driver application table 12 ac characteristics for seg ment driver application v dd = 5 v r 10%; v ss = 0 v; t amb = -30 q c to +85 q c. symbol parameter vdd=5v10% vdd=3v10% test condition unit min. typ max. min. max. t cy clock cycle time 125 250 duty=50% ns t wck clock pulse width 45 95 ns t r , t f clock rise/fall time ns t ds data set-up time ns t dh data hold time 30 65 ns t cs clock set-up time 80 120 ns t ch clock hold time ns t phl propagation delay time (elb output) ns t phl propagation delay time (erb output) 60 125 ns t psu elb set-up time elb input ns t psu erb set-up time erb input ns t wdl dispoffb low pulse width 1200 1200 ns t cd dispoffb clear time 100 100 ns t pd1 m - out propagation delay time c l = 15 pf ns t pd2 cl1 - out propagation delay time 1000 1200 c l = 15 pf ns t pd3 dispoffb - out propagation delay time c l = 15 pf ns 8.5 ac characteristics for common driver application table 13 ac characteristics for common driver application v dd = 5 v r 10%; v ss = 0 v; t amb = -30 q c to +85 q c. symbol parameter vdd=5v10% vdd=3v10% test condition unit min. typ max. min. max. t cy clock cycle time 250 500 duty=50% ns t wck clock pulse width 45 95 ns t r , t f clock rise/fall time ns t ds data set-up time ns t dh data hold time 30 65 ns t wdl dispoffb low pulse width 1200 1200 ns t cd dispoffb clear time 100 100 ns t dl output delay time c l = 15 pf ns
2005 sep 29 21 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics t pd1 m - out propagation delay time 1000 1200 c l = 15 pf ns t pd2 cl1 - out propagation delay time 1000 1200 c l = 15 pf ns t pd3 dispoffb - out propagation delay time 1000 1200 c l = 15 pf ns symbol parameter vdd=5v10% vdd=3v10% test condition unit min. typ max. min. max.
2005 sep 29 22 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 9 timing diagram 9.1 timing diagram for segment driver application fig.18 timing diagram for segment driver application. 0.8vdd 0.2vdd 0.8vdd 0.2vdd cl1 t ch 0.8vdd 0.2vdd t cs t wck 0.2vdd t f 0.8vdd 0.2vdd 0.8vdd t wck t r t cy t ds 0.8vdd 0.8vdd 0.2vdd 0.2vdd t wdl t cd 0.2vdd t phl t psu 0.2vdd 0.2vdd cl1 cl2 d1_sid ~ d4_dr dispoffb cl2 12 3 1920 0.8vdd elb,erb (output1) elb,erb (input 2) 0.8vdd 0.2vdd 0.2vdd 0.8vdd 0.2vdd t pd1 t pd2 dispoffb sc1-sc80 (latched data) cl1 m twck t dh t pd3
2005 sep 29 23 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 9.2 timing diagram for common driver application fig.19 timing diagram for common driver application. 0.8vdd 0.2vdd t cy t f 0.8vdd 0.2vdd t wck t r 0.8vdd 0.2vdd t wdl t cd cl1 dispoffb 0.8vdd 0.2vdd 0.2vdd 0.8vdd 0.2vdd t pd1 t pd2 dispoffb sc1-sc80 (latched data) cl1 m t f t dh t ds 0.8vdd 0.2vdd 0.8vdd 0.2vdd do di t pd3 t dl note: when in single-type interface mode: (1) di=> d2_dl (shl=l), d4_dr (shl=h). (2) do=> d4_dr (shl=l), d2_dl (shl=h). when in dual-type interface mode: (3) di=>d2_dl and d3_dm (shl=l), d4_dr and d3_dm (shl=h) (4) do=>d4_dr (shl=l), d2_dl (shl=h). see note below see note below
2005 sep 29 24 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 10 power down function to reduce power consumption, the s dn8080g is sequentially enabled via powe r down mode, when used in cascade in segment driver application. table 14 power down function shl enable input enable output current driver status ( the driver being enabled) status of other drivers l erb elb while erb=low, current driver is enabled. disabled. h elb erb while elb=low, current driver is enabled. disabled. . note 1. power down function is not available w hen the SDN8080G is used as a common driver. fig.20 timing diagram for power down function. notes: (1) shl=high (elb=input, erb=output). current SDN8080G?s erb output must be connected to the next SDN8080G?s elb input. (2) when in 4-bit parallel interface mode: n=20. (3) when in 1-bit serial interface mode: n=80. 12 n-1n 12 n-1 n-1 2 1 n n-1 2 1 n n-1 2 1 n cl1 cl2 elb1(input1) (output1/input2) erb1/elb2 (output2/input3) erb2/elb3 (output3/input4) erb3/elb4 erb4(output4) 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99
2005 sep 29 25 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 11 operation timing diagram 11.1 4-bit parallel mode interface (segment driver) 11.1.1 w hen shl=low fig.21 when shl=low. sc5 sc1 sc77 sc73 sc69 sc5 sc1 sc77 sc73 cl2 d1_sid sc6 sc2 sc78 sc74 sc70 sc6 sc2 sc78 sc74 d2_dl sc7 sc3 sc79 sc75 sc71 sc7 sc3 sc79 sc75 d3_dm sc8 sc4 sc80 sc76 sc72 sc8 sc4 sc80 sc76 d4_dr sc1-sc80 cl1 elb (output) erb (input) 19 20 1 2 3 19 20 1 2 11.1.2 w hen shl=high fig.22 when shl=high sc76 sc80 sc4 sc8 sc12 sc76 sc80 sc4 sc8 cl2 d1_sid sc75 sc79 sc3 sc7 sc11 sc75 sc79 sc3 sc7 d2_dl sc74 sc78 sc2 sc6 sc10 sc74 sc78 sc2 sc6 d3_dm sc73 sc77 sc1 sc5 sc9 sc73 sc77 sc1 sc5 d4_dr sc1-sc80 cl1 erb (output) elb (input) 19 20 12 3 19 20 1 2
2005 sep 29 26 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 11.2 1-bit serial mode interface (segment driver) 11.2.1 w hen shl=low fig.23 shl=low, 1-bit serial mode interface. sc2 sc1 sc80 sc79 sc78 sc2 sc1 sc80 sc79 cl2 d1_sid sc1-sc80 cl1 elb (output) erb (input) 79 80 12 3 79 80 12 11.2.2 w hen shl=high fig.24 shl=high, 1-bit serial mode interface. sc79 sc80 sc1 sc2 sc3 sc79 sc80 sc1 sc2 cl2 d1_sid sc1-sc80 cl1 erb (output) elb (input) 79 80 12 3 79 80 12
2005 sep 29 27 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 11.3 single type interface mode (common driver) 11.3.1 w hen shl=low fig.25 shl=low, single-type interface mode. cl1 d2_dl d4_dr com_data1 com_data2 com_data3 79 80 1 2 79 80 com_data79 com_data80 1 2 common area of current driver 11.3.2 w hen shl=high fig.26 shl=high, single-type interface mode. cl1 d4_dr d2_dl com_data1 com_data2 com_data3 79 80 1 2 79 80 com_data79 com_data80 2 1 common area of current driver
2005 sep 29 28 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 11.4 dual type interface mode (common driver) 11.4.1 w hen shl=low fig.27 shl=low, dual-type interface mode. cl1 d2_dl d3_dm d4_dr com_data1 com_data2 com_data3 com_data39 com_data40 com_data41 com_data42 com_data43 com_data79 com_data80 1 2 3 39 40 1 2 3 39 40 11.4.2 w hen shl=high fig.28 shl=high, dual-type interface mode. cl1 d2_dl d3_dm d4_dr com_data1 com_data2 com_data3 com_data39 com_data40 com_data41 com_data42 com_data43 com_data79 com_data80 1 2 3 39 40 1 2 3 39 40
2005 sep 29 29 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 11.5 common/segment driver timing (1/200 duty) 1 2 18 19 20 1 cl1 latched data(seg) m com_data1 com_data199 com_data200 v0 com1 v4 v5 v0 v1 com199 v4 v5 v0 v1 com200 v4 v5 seg_data1 v0 v1 v2 v3 v4 v5 seg1 cl2 cl1 d1~d4 m 199 200 1 200 1 199 200 1 199 200 fig.29 common/segment driver timing( 1/200 duty). lathced data enable out v1
2005 sep 29 30 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 12 application diagrams 12.1 4-bit parallel interface mode (80-outputs segment driver) 12.1.1 l ower view (shl=low, ams=low) fig.30 lower view (shl=low, ams=low). lcd panel sc80 erb cs ams shl sc1 elb d1_sid ~ d4_dr sc80 erb cs ams shl sc1 elb d1_sid ~ d4_dr sc80 erb cs ams shl sc1 elb d1_sid ~ d4_dr 4 4 4 4-bit parallel data input s1 s80 s81 s160 sn sn+79 12.1.2 u pper view (shl=high, ams=low) fig.31 upper view (shl=high, ams=low). lcd panel sc80 erb cs ams shl elb sc1 d1_sid ~ d4_dr sc80 erb cs ams shl elb sc1 sc80 erb cs ams shl elb sc1 4 4 4 4-bit data input parallel s1 s80 s81 s160 sn sn+79 d1_sid ~ d4_dr d1_sid ~ d4_dr vdd vdd vdd
2005 sep 29 31 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 12.2 1-bit serial interface mode (80-outputs segment driver) 12.2.1 l ower view (shl=low, ams=high) fig.32 lower view (shl=l, ams=h). lcd panel sc80 erb cs ams shl sc1 elb d2_dl~ d4_dr d1_sid sc80 erb cs ams shl sc1 elb d2_dl~ d4_dr d1_sid sc80 erb cs ams shl sc1 elb d2_dl~ d4_dr d1_sid 1-bit data input serial s1 s80 s81 s160 sn sn+79 12.2.2 u pper view (shl=high, ams=high) fig.33 upper view (shl=high, ams=high). lcd panel sc80 erb cs ams shl sc1 d2_dl~ d4_dr d1_sid sc80 erb cs ams shl sc1 d2_dl~ d4_dr d1_sid sc80 erb cs ams shl sc1 d2_dl~ d4_dr d1_sid elb elb elb 1-bit data input serial s1 s80 s81 s160 sn sn+79
2005 sep 29 32 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 12.3 single type interface mode (80-outputs common driver) fig.34 single-type interface mode (80-outputs common driver). sc1 sc80 ams d4_dr cs sc1 sc80 ams d4_dr cs sc1 sc80 ams d4_dr cs input data c1 c80 c81 c160 c161 c240 lcd panel vdd vdd vdd (common scan pulse) shl d2_dl shl d2_dl shl d2_dl
2005 sep 29 33 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 12.4 dual type interface mode (40-outputs + 40-outputs common driver) fig.35 dual-type interface mode (4 0-outputs + 40-outputs common driver). note: in this mode (dual-type common mode), duty ratio can be reduced to half. in this example, 1/200 duty can be used to drive 400 common lcd panel. sc1 s80 ams d4_dr cs sc1 sc80 ams d4_dr cs sc1 sc80 ams d4_dr cs sc1 sc80 ams d4_dr cs sc1 sc80 ams d4_dr cs input data 1 input data 2 c1 c80 c81 c160 c241 c320 c321 c400 c200 c201 c161 c240 lcd panel (1/2) lcd panel (2/2) sc41 sc40 d3_dm (common scan pulse) vdd vdd vdd vdd vdd (common scan pulse) shl d2_dl shl d2_dl shl d2_dl shl d2_dl shl d2_dl
2005 sep 29 34 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 12.5 typical application circuit fig.36 typical application circuit m d4_dr dispoffb sc80 shl cs com1 com80 SDN8080G m d4_dr dispoffb sc80 shl cs ams SDN8080G 240 x 240 lcd module dispoffb cl1 sc1 sc80 shl cs - elb erb m cl2 ams seg1 - seg80 SDN8080G dispoffb cl1 sc1 sc80 shl cs elb erb m cl2 ams seg1 - seg80 SDN8080G v0-v5 dispoffb cl1 sc1 sc80 shl cs elb erb m cl2 ams seg1 - seg80 SDN8080G s1 s80 s81 s160 s161 s240 c1 c80 c81 c160 4 4 4 4 4 4 4 vo~v5 ams vo~v5 ~ com1 com80 ~ m d4_dr dispoffb sc80 cs ams SDN8080G c161 c240 4 com1 com80 ~ v0~v5 cl1 d2_dl shl sc1 cl1 cl2 d1~~d4 com_data frame(m) dispoffb controller cl1 d2_dl sc1 cl1 d2_dl sc1 d1_sid_d4_dr v0-v5 d1_sid_d4_dr v0-v5 d1_sid_d4_dr v1 v2 v3 v4 v5 vdd vee vss r r (n-4)r r r 4 v0
2005 sep 29 35 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 13 pin circuits table 15 mos-level schematics of all input, output, and i/o pins. symbol input/ output circuit notes v0, v12, v43, v5, sc1~sc80 i/o scn n= 1 ~ 80 v0 v12 v43 v5 vee vdd en1 en2 en3 en4 vdd vdd vdd vee vee vee cs, m, dispoffb, shl, ams, cl1 input vss vdd vss vdd cl2, d1_sid, d3_dm input vss vdd vss vdd vdd en
2005 sep 29 36 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics elb, erb i/o vss vdd vss vdd vdd en data vss vdd enable d2_dl, d4_dr i/o vss vdd vss vdd data vss vdd enable symbol input/ output circuit notes
2005 sep 29 37 of 40 data sheet (v6) 80-outputs common/segment driver SDN8080G avant electronics 14 application notes application information is provided in another document. please contact avant electronics for application information.
stn lcd driver data sheet (v6) 80-outputs common/segm ent driver SDN8080G 2005 sep 29 38 15 package information SDN8080G lqfp100 package outline drawing
2005 sep 29 39 stn lcd driver data sheet (v6) 80-outputs common/segm ent driver SDN8080G 16 soldering 16.1 introduction there is no soldering method that is ideal for all ic package s. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circui ts with high components densities. in thes e situations reflow soldering is often recommended. this text gives a very brief description to a complex technology. a more in-depth description of soldering ics can be provided to our customers upon request. 16.2 reflow soldering reflow soldering techniques ar e suitable for all qfp packages. the choice of heating method may be infl uenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolute ly dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, please contact avant for drypack information. reflow soldering requires solder paste (a suspension of fi ne solder particles, flux and bi nding agent) to be applied to the printed-circuit board by screen prin ting, stencilling or pressure-syri nge dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds, depending on heating method. typica l reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and ev aporate the binding agent. preheating duration: 45 minutes at 45 c. 16.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possib ility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: ? a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. ? the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfe r, or syringe dispensing. the package ca n be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwelling time is 4 seconds at 250 c. a mildly-activated flux will elimi nate the need for removal of corrosiv e residues in most applications. 16.4 repairing soldered joints fix the component by first soldering two diagonally- oppos ite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2005 sep 29 40 stn lcd driver data sheet (v6) 80-outputs common/segm ent driver SDN8080G 17 life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury . avant customers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify avant for any damages resulting from such improper use or sale.

▲Up To Search▲

Price & Availability of SDN8080G

	To Download SDN8080G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .